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general description the max1907a/MAX1981A are single-phase, quick- pwm master controllers for imvp-iv cpu core sup- plies. multi-phase operation is achieved using a quick-pwm slave controller (max1980). multiphase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. the max1907a/ MAX1981A include active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. the max1907a/MAX1981A are intended for two differ- ent notebook cpu core applications: either bucking down the battery directly, or 5v system supply to create the core voltage. the single-stage conversion method allows these devices to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down the 5v system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. the max1907a/MAX1981A meet the imvp-iv specifica- tions and include logic to interface with the cpu power good signals from the v ccp and v ccmch rails within the system. the regulator features power-up sequencing, automatically ramping up to the intel-specified boot volt- age. the max1907a/MAX1981A feature independent four-level logic inputs for setting the boot voltage (b0?2) and the suspend voltage (s0?2). the max1907a/MAX1981A include output undervoltage protection, thermal protection, and system power-ok (syspok) input/output. when any of these protection fea- tures detect a fault, the max1907a/MAX1981A immedi- ately shut down. additionally, the max1907a includes overvoltage protection. the max1907a/MAX1981A are available in a thin 40-pin qfn package. applications imvp-iv notebook computers single-phase cpu core supply multiphase cpu core supply voltage-positioned step-down converters servers/desktop computers features ? quick-pwm master controllers ? multiphase conversion with slave controller (max1980) ? active voltage positioning with adjustable gain and offset ? adjustable slew rate control ? 0.75% v out accuracy over line, load, and temperature ? 6-bit on-board dac (16mv increments) ? 0.700v to 1.708v output adjust range ? selectable 200khz/300khz/550khz/1000khz switching frequency ? 2v to 28v battery input voltage range ? drive large synchronous rectifier mosfets ? output overvoltage protection (max1907a only) ? undervoltage and thermal fault protection ? power sequencing and selectable boot voltage ? low-profile 40-pin thin qfn, 6mm ? ? 6mm package max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ________________________________________________________________ maxim integrated products 1 ordering information 40-pin, 6mm x 6mm thin qfn 40 39 38 37 36 1 2 3 4 5 11 12 13 14 15 26 27 28 29 30 top view max1907a MAX1981A v dd b0 b1 b2 s0 s1 6 s2 7 shdn 8 ref 9 ilim 10 v cc dl ddo d0 25 d1 24 d2 23 d3 22 d4 21 d5 pgnd fb 16 oain+ 17 oain- 18 csp 19 csn 20 dpslp neg pos cc gnd ton time clken imvpok syspok 35 sus 34 v+ 33 dh 32 bst 31 lx pin configuration 19-2678; rev 0; 9/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. quick-pwm is a trademark of maxim integrated products, inc. imvp-iv is a trademark of intel corp. part temp range pin-package max1907a etl -40 c to +100 c 40- qfn thi n 6m m x 6m m MAX1981A etl -40 c to +100 c 40- qfn thi n 6m m x 6m m typical operating circuit appears at end of data sheet.
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0= s0 = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = 0c to +85c , unless otherwise specified.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +30v v cc , v dd to gnd .....................................................-0.3v to +6v syspok, imvpok, clken to gnd .........................-0.3v to +6v dpslp , sus, d0?5 to gnd ...................................-0.3v to +6v ref, ilim, csp, csn to gnd.....................-0.3v to (v cc + 0.3v) fb, pos, neg, oain+, cc oain- to gnd.........................................-0.3v to (v cc + 0.3v) b0?2, s0?2, ton, time to gnd ..........................................-0.3v to (v cc + 0.3v) dl, ddo , to pgnd.....................................-0.3v to (v dd + 0.3v) dh to lx ....................................................-0.3v to (v bst + 0.3v) shdn to gnd...........................................................-0.3 to +18v bst to gnd ..............................................................-0.3 to +36v lx to bst..................................................................-6v to +0.3v gnd to pgnd .......................................................-0.3v to +0.3v ref short-circuit duration .........................................continuous continuous power dissipation 40-pin 6mm ? 6mm thin qfn (derate 26.3mw/? above +70?) .............................2105mw operating temperature range .........................-40? to +100? junction temperature ......................................................+150? storage temperature.........................................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units pwm controller battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v dac codes from 1.276v to 1.708v -0.75 +0.75 dac codes from 0.844v to 1.260v -1.25 +1.25 dc output voltage accuracy v+ = 4.5v to 28v, includes load regulation error dac codes from 0.444v to 0.828v -3.0 +3.0 % line regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v 5 mv i fb fb -1 +1 input bias current i pos , i neg pos, neg -0.2 +0.2 ? pos, neg common-mode range dpslp = gnd 0 2 v pos, neg differential range v pos - v neg , dpslp = gnd -200 +200 mv pos, neg offset gain a off v fb /(v pos - v neg ), (v pos - v neg ) = 100mv, dpslp = gnd 0.95 1.00 1.05 mv/mv pos, neg enable time measured from the time dpslp goes low to the time in which pos, neg affect a change in the set point (v dac ) 0.1 ? 640khz nominal, r time = 23.5k 58 64 70 khz
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0= s0 = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = 0c to +85c , unless otherwise specified.) parameter symbol conditions min typ max units v+ = 5v, v fb = 1.2v, ton = gnd (1000khz) 250 270 290 ton = ref (550khz) 165 190 215 ton = open (300khz) 320 355 390 on-time (note 1) t on v+ = 12v, v fb = 1.2v ton = v cc = (200khz) 465 515 565 ns ton = gnd (1000khz) 300 375 ns minimum off-time (note 1) t off ( min ) ton = v cc , open or ref (200khz, 300khz, or 550khz) 400 475 ns ddo delay time t ddo measured from the time fb reaches the voltage set by s0?2, clock speed set by r time 32 clks skip delay time t skip measured from the time when ddo is asserted to the time in which the controller begins pulse-skipping operation 30 clks bias and reference quiescent supply current (v cc ) i cc measured at v cc , fb forced above the regulation point 1.3 2.0 ma quiescent supply current (v dd ) i dd measured at v dd , fb forced above the regulation 0.1 5 a quiescent battery supply current (v+) i v+ measured at v+ 21 40 ? shutdown supply current (v cc ) measured at v cc , shdn = gnd 0.1 5 a shutdown supply current (v dd ) measured at v dd , shdn = gnd 0.1 5 a shutdown battery supply current (v+) measured at v+, shdn = gnd, v cc = v dd = 0 or 5v 0.1 5 a reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.990 2.000 2.010 v reference load regulation v ref i ref = -10? to 100? -10 +10 mv fault protection output overvoltage protection threshold measured at fb with respect to unloaded output voltage, dac code = 0.7v to 1.708v 13 16 19 % output overvoltage propagation delay t ovp fb forced 2% above trip threshold 10 ? output undervoltage protection threshold with respect to unloaded output voltage dac code = 0.7v to 1.708v 67 70 73 % output undervoltage propagation delay t uvp fb forced 2% below trip threshold 10 ? output fault blanking time t blank the clock speed is set by r time (note 2) 32 clks
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0= s0 = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = 0c to +85c , unless otherwise specified.) parameter symbol conditions min typ max units lower threshold (undervoltage) -12 -10 -8 imvpok, clken threshold syspok = v cc ; measured at fb with respect to unloaded output voltage upper threshold (overvoltage) 81012 % clken delay t clken fb in regulation, measured from the rising edge of syspok 30 50 90 ? imvpok, clken transition blanking time measured from the time when fb reaches the voltage set by the dac code, clock speed set by r time 32 clks imvpok delay t imvpok fb in regulation, measured from the falling edge of clken 357ms imvpok, clken , output low voltage i sink = 3ma 0.3 v imvpok, clken , leakage current high state, impok, clken forced to 5.5v 1 a v cc undervoltage lockout threshold v uvlo ( vcc ) rising edge, hysteresis = 20mv, pwm disabled below this level 4.0 4.4 v thermal shutdown threshold hysteresis = 10? 160 ? current limit current-limit threshold voltage (positive, default) csp - csn, ilim = v cc 47 50 53 mv v ilim = 0.3v 27 30 33 current-limit threshold voltage (positive, adjustable) csp - csn v ilim = 1v 97 100 103 mv current-limit threshold voltage (negative) csp - csn; ilim = v cc , sus = gnd and dpslp = v cc -68 -63 -58 mv current-limit threshold voltage (zero crossing) gnd - lx; sus = v cc or dpslp = gnd 4 mv csp, csn input ranges 02v csp, csn input current v csp = v csn = 0 to 5v -1 +1 ? ilim input current v ilim = 0 to 5v 0.01 200 na current-limit default switchover threshold ilim 3 v cc - 1 v cc - 0.4 v gate drivers dh gate-driver on-resistance r on ( dh ) bst - lx forced to 5v 1.2 4.0 high state (pullup) 1.2 4.0 dl gate-driver on-resistance r on ( dl ) low state (pulldown) 0.5 1.5 dh gate-driver source/sink current dh forced to 2.5v, bst - lx forced to 5v 1.6 a dl gate-driver sink current dl forced to 2.5v 4 a
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0= s0 = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = 0c to +85c , unless otherwise specified.) parameter symbol conditions min typ max units dl gate-driver source current dl forced to 2.5v 2 a dl rising 35 dead time dh rising 26 ns voltage-positioning amplifier input offset voltage v os v cm = 0 -1 +1 mv input bias current i bias oain+, oain- <0.1 200 na op amp disable threshold oain- 3 v cc - 1 v cc - 0.4 v common-mode input voltage range v cm guaranteed by cmrr test 0 2.5 v common-mode rejection ratio cmrr v oain+ = v oain- = 0 to 2.5v 70 115 db power-supply rejection ratio psrr v cc = 4.5v to 5.5v 75 100 db large-signal voltage gain a oa r l = 1k to v cc /2 80 112 v cc - v oh 100 300 output voltage swing | v oain+ - v oain- | 10mv, r l = 1k to v cc /2 v ol 70 200 mv input capacitance 11 pf gain-bandwidth product 3 mhz slew rate 0.3 v/? capacitive-load stability no sustained oscillations 400 pf logic and i/o logic input high voltage v ih sus, dpslp , shdn , syspok 2.4 v logic input low voltage v il sus, dpslp , shdn , syspok 0.8 v logic input current sus, dpslp , shdn , syspok -1 +1 ? shdn no fault threshold to enable no-fault mode 12 15 v dac input high voltage v vid ( high ) d0?5 0.7 v dac input low voltage v vid ( low ) d0?5 0.3 v dac input current d0?5 -1 +1 ? driver-disable output high voltage ddo , i load = 1ma 2.4 v driver-disable output low voltage ddo , i load = 1ma 0.3 v high v cc - 0. 4 open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, s0?2, b0?2 low 0.5 v four-level input current ton, s0?2, b0?2 forced to gnd or v cc -3 +3 ?
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 6 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0 = so = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = -40c to +100c , unless otherwise specified.) parameter symbol conditions min typ max units battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v dac codes from 1.276v to 1.708v -1.00 +1.00 dac codes from 0.844v to 1.260v -1.5 +1.5 dc output voltage accuracy v+ = 4.5v to 28v, includes load regulation error dac codes from 0.444v to 0.828v -3.5 +3.5 % pos, neg offset gain a off v fb /(v pos - v neg ), (v pos - v neg ) = 100mv, dpslp = gnd 0.95 1.05 mv/mv 640khz nominal, r time = 23.5k 58 70 khz v+ = 5v, v fb = 1.2v, ton = gnd (1000khz) 250 290 ton = ref (550khz) 165 215 ton = open (300khz) 320 390 on-time (note 1) t on v+ = 12v, v fb = 1.2v ton = v cc (200khz) 465 565 ns ton = gnd (1000khz) 375 ns minimum off-time (note 1) t off ( min ) ton = v cc , open, or ref (200khz, 300khz, or 550khz) 475 ns bias and reference quiescent supply current (v cc ) i cc measured at v cc , fb forced above the regulation point 2.0 ma quiescent supply current (v dd ) i dd measured at v dd , fb forced above the regulation 20 ? quiescent battery supply current (v+) i v+ measured at v+ 40 ? shutdown supply current (v cc ) measured at v cc , shdn = gnd 20 ? shutdown supply current (v dd ) measured at v dd , shdn = gnd 20 ? shutdown battery supply current (v+) measured at v+, shdn = gnd, v cc = v dd = 0 or 5v 20 ?
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0 = so = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = -40c to +100c , unless otherwise specified.) parameter symbol conditions min typ max units reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.985 2.015 v fault protection output overvoltage protection threshold measured at fb with respect to unloaded output voltage 13 19 % output undervoltage protection threshold with respect to unloaded output voltage 67 73 % lower threshold (undervoltage) -12 -8 % imvpok, clken threshold syspok = v cc ; measured at fb with respect to unloaded output voltage upper threshold (overvoltage) +8 +12 % clken delay t clken fb in regulation, measured from the rising edge of syspok 30 ? imvpok delay t imvpok fb in regulation, measured from the falling edge of clken 3ms v cc undervoltage lockout threshold v uvlo ( vcc ) rising edge, hysteresis = 20mv, pwm disabled below this level 3.95 4.45 v current limit current-limit threshold voltage (positive, default) csp - csn, ilim = v cc 45 55 mv v ilim = 0.3v 25 35 current-limit threshold voltage (positive, adjustable) csp - csn v ilim = 2v (ref) 95 105 mv current-limit threshold voltage (negative) csp - csn; ilim = v cc , sus = gnd and dpslp = v cc -70 -56 mv gate drivers dh gate-driver on-resistance r on ( dh ) bst - lx forced to 5v 4.5 high state (pullup) 4.5 dl gate-driver on-resistance r on ( dl ) low state (pulldown) 2.0 voltage-positioning amplifier input offset voltage v os v cm = 0 -2 +2 mv v cc - v oh 300 output voltage swing | v oain+ - v oain- | 10mv, r l = 1k to v cc /2 v ol 200 mv
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v bi = v oain - = 5v, v fb = v csp = v csn = v oain+ = v neg = v pos = 1.26v, ilim = v cc , sus = d5 = d1= d0 = so = s1 = s2 = b0 = gnd, v d4 = v d3 = v d2 = 1v, v b2 = 2v. t a = -40c to +100c , unless otherwise specified.) note 1: on-time specifications are measured from 50% to 50% at the dh pin, with lx forced to gnd, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times may be different due to mosfet switching speeds. note 2: the output fault blanking time is measured from the time when fb reaches the regulation voltage set by the dac code. during power-up, the regulation voltage is set by the boot dac code (b0?2). during normal operation (sus = low), the regulation voltage is set by the vid dac inputs (d0?5). during suspend mode (sus = high), the regulation voltage is set by the suspend dac inputs (s0?2). note 3: specifications to t a = -40? to +100? are guaranteed by design and are not production tested. parameter symbol conditions min max units v cc ?v oh 300 output voltage swing | v oain+ ?v oain- | 10mv, r l = 1k to v cc /2 v ol 200 logic and i/o dac input high voltage v vid ( high ) d0?5 0.7 v dac input low voltage v vid ( low ) d0?5 0.3 v high v cc - 0.4 open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, s0?2, b0?2 low 0.5 v
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) _______________________________________________________________________________________ 9 typical operating characteristics (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, b0?2 set to 1.276v, s0?2 set to 0.748v.) voltage-positioned output vs. load current (v out = 1.436v) max1907a/81a toc01 load current (a) output voltage (v) 40 30 20 10 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.28 050 efficiency vs. load current (v out = 1.436v) max1907a/81a toc02 load current (a) efficiency (%) 10 1 60 70 80 90 100 50 0.1 100 v in = 20v v in = 12v v in = 5v v in = 8v max1907a/81a toc03 load current (a) output voltage (v) 25 20 15 10 5 0.76 0.78 0.80 0.82 0.84 0.86 0.74 030 voltage-positioned output vs. load current (v out = 0.844v) efficiency vs. load current (v out = 0.844v) max1907a/81a toc04 load current (a) efficiency (%) 10 1 60 70 80 90 100 50 0.1 100 v in = 20v v in = 12v v in = 5v v in = 8v max1907a/81a toc05 load current (a) output voltage (v) 20 15 10 5 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0.77 0.67 025 voltage-positioned output vs. load current (v out = 0.748v) sus = v cc efficiency vs. load current (v out = 0.748v) max1907a/81a toc06 load current (a) efficiency (%) 10 1 60 70 80 90 100 50 0.1 100 v in = 20v v in = 12v v in = 5v v in = 8v sus = v cc . output voltage shift vs. temperature max1907a/81a toc07 temperature ( c) v out (mv) 80 60 40 20 0 -20 -2 -1 0 1 2 3 -3 -40 100 no load 20a load frequency vs. load current max1907a/81a toc08 load current (a) frequency (khz) 25 20 5 10 15 50 100 150 200 250 300 350 400 0 030 forced pwm skip operation single phase frequency vs. input voltage max1907a/81a toc09 input voltage (v) frequency (khz) 25 20 15 10 5 250 270 290 310 330 350 230 030 single phase i out = 20a no load
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 10 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, b0?2 set to 1.276v, s0?2 set to 0.748v.) no-load supply current vs. input voltage (pulse skipping) max1907a/81a toc12 input voltage (v) supply current (ma) 25 20 15 10 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 030 max1907a/MAX1981A only dpslp = gnd i cc + i dd i+ output offset voltage vs. pos-neg differential voltage max1907a/81a toc14 pos-neg differential voltage (mv) output offset voltage (mv) 400 200 0 -200 -400 -400 -200 0 200 400 600 -600 -600 600 1.260v output voltage distribution max1907a/81a toc15 output voltage (v) sample percentage (%) 1.265 1.260 1.255 10 20 30 40 50 0 1.250 1.270 reference voltage distribution max1907a/81a toc16 reference voltage (v) sample percentage (%) 2.003 2.001 1.999 1.997 5 10 15 20 25 0 1.995 2.005 pos-neg offset gain distribution max1907a/81a toc17 pos-neg offset gain sample percentage (%) 1.01 1.00 0.99 10 20 30 40 50 60 0 0.98 1.02 60 -40 0.1 10 100 1000 1 10,000 voltage-positioning amplifier gain and phase vs. frequency -20 -10 0 -30 max1907a/81a toc18 frequency (khz) gain (db) phase (degrees) 10 20 30 40 50 180 -180 -108 -72 -36 -144 0 36 72 108 144 gain phase frequency vs. temperature max1907a/81a toc10 temperature ( c) frequency (khz) 80 60 40 20 0 -20 270 290 310 330 350 250 -40 100 20a load no load single phase v out = 1.436v output current at current limit vs. temperature max1907a/81a toc11 temperature ( c) maximum load current (a) 80 60 40 20 0 -20 21 22 23 24 25 20 -40 100 single phase no-load supply current vs. input voltage (forced-pwm mode) max1907a/81a toc12 input voltage (v) supply current (ma) 25 20 15 10 5 5 10 15 20 25 30 35 0 030 i cc = i dd i+ max1907a/MAX1981A only
soft-start max1907a/81a toc22 100 s/div a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 0.844v, 500mv/div c. i lm , 10a/div d. i ls , 10a/div 80m load 0 0 0 0 d c b a v boot v id impvok delay max1907a/81a toc23 1ms/div a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 0.844v, 500mv/div c. impvok 5v/div d. clken, 5v/div 0 0 0 0 d c b a v boot power-up sequence (highest frequency) max1907a/81a toc20 0 0 0 0 d c b a 100 s/div a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 1.436v, 500mv/div c. ddo, 5v/div d. clken, 5v/div v boot v id power-up sequence (lowest frequency) max1907a/81a toc21 100 s/div a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 0.844v, 500mv/div c. ddo, 5v/div d. clken, 5v/div no load 0 0 0 0 d c b a v boot v id max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 11 vps amplifier offset voltage vs. common-mode voltage max1907a/81a toc19 common-mode voltage (v) offset voltage ( v) 4 3 2 1 20 40 60 80 100 120 140 160 180 0 05 vps amplifier disabled shutdown sequence max1907a/81a toc24 100 s/div a. v shdn = 0 to 5v, 5v/div b. v out = 1.436v to 0, 1v/div c. impvok 5v/div d. clken, 5v/div e. ddo, 5v/div 0 0 0 0 0 1.436v d e c b a typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, b0?2 set to 1.276v, s0?2 set to 0.748v.)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 12 ______________________________________________________________________________________ soft shutdown max1907a/81a toc25 40 s/div a. v shdn = 0 to 5v, 5v/div b. v out = 0.844v to 0, 1v/div c. i lm , 10a/div d. i ls ,10a/div 80m load 0 0 0 0 d c b a entering deep-sleep mode max1907a/81a toc26 20 s/div a. v dpslp = 0 to 5v, 5v/div b. v out = 1.436v to 1.398v, 50mv/div c. max1907a/MAX1981A lx, 10v/div d. max1980 lx, 10v/div sus = gnd, i out = 1.0a 0 0 1.398v 1.436v 0 d c b a exiting deep-sleep mode max1907a/81a toc27 20 s/div a. v dpslp = 0 to 5v, 5v/div b. v out = 1.398v to 1.436v, 50mv/div c. max1907a/MAX1981A lx, 10v/div d. max1980 lx, 10v/div sus = gnd, i out = 1.0a 0 0 1.398v 1.436v 0 d c b a entering suspend mode max1907a/81a toc28 20 s/div a. v sus = 0 to 5v, 5v/div b. v out = 1.398v to 0.748v, 500mv/div c. max1907a/MAX1981A lx, 10v/div d. max1980 lx, 10v/div dpslp = gnd, i out = 0.5a 0 0 0.748v 1.398v 0 d c b a exiting suspend mode max1907a/81a toc29 20 s/div a. v sus = 0 to 5v, 5v/div b. v out = 0.748v to 1.398v, 500mv/div c. max1907a/MAX1981A lx, 10v/div d. max1980 lx, 10v/div dpslp = gnd, i out = 0.5a 0 0 0.748v 1.398v 0 d c b a load transient (lowest frequency) max1907a/81a toc30 20 s/div a. i out = 0 to 10a, 10a/div b. v out = 0.844v (no load), 50mv/div c. i lm , 10a/div d. i ls , 10a/div 0 0 0.844v 0 10a d c b a typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, b0?2 set to 1.276v, s0?2 set to 0.748v.)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 13 load transient (highest frequency) max1907a/81a toc31 20 s/div a. i out = 0 to 30a, 20a/div b. v out = 1.436v (no load), 100mv/div c. i lm , 10a/div d. i ls , 10a/div 0 0 1.436v 0 30a d c b a dynamic vid transition (do = 16mv) max1907a/81a toc32 20 s/div a. v do = 0 to 1v, 1v/div b. v out = 1.436v to 1.420v,, 20mv/div c. i lm , 10a/div d. i ls , 10a/div 0 0 1.436v 0 d c b a dynamic vid transition (d3 = 128mv) max1907a/81a toc33 40 s/div a. v d3 = 0 to 1v, 1v/div b. v out = 1.436v to 1.308v, 100mv/div c. i lm , 10a/div d. i ls , 10a/div 0 0 1.436v 1.308v 0 d c b a typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, b0?2 set to 1.276v, s0?2 set to 0.748v.)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 14 ______________________________________________________________________________________ pin description pin name function 1, 2, 3 b0?2 boot-mode voltage select inputs. b0?2 are four-level digital inputs that select the boot-mode vid code (table 6) for the boot-mode multiplexer inputs. during power-up, the boot-mode vid code is delivered to the dac (see the internal multiplexers section). 4, 5, 6 s0?2 suspend-mode voltage select inputs. s0?2 are four-level digital inputs that select the suspend-mode vid code (table 5) for the suspend-mode multiplexer inputs. if sus is high, the suspend-mode vid code is delivered to the dac (see the internal multiplexers section). 7 shdn shutdown control input. this input cannot withstand the battery voltage. connect to v cc for normal operation. connect to ground to put the ic into its 10? (max) shutdown state. during the transition from normal operation to shutdown the output voltage is ramped down at the output voltage slew rate programmed by the time pin. in shutdown mode, dl is forced to v dd to clamp the output to ground. forcing shdn to 12v~15v disables both overvoltage protection and undervoltage protection circuits, and clears the fault latch. do not connect shdn to >15v. 8 ref 2v reference output. bypass to gnd with 0.22? or greater ceramic capacitor. the reference can source 50? for external loads. loading ref degrades output voltage accuracy according to the ref load regulation error. 9 ilim current-limit adjustment. the current-limit threshold defaults to 50mv if ilim is tied to v cc . in adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ilim over a 100mv to 1.5v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. 10 v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage (4.5v to 5.5v) with a series 10 resistor. bypass to gnd with a 1? or greater ceramic capacitor, as close to the ic as possible. 11 gnd analog ground 12 cc integrator capacitor connection. connect a 47pf to 1000pf (270pf typ) capacitor from cc to gnd to set the integration time constant. 13 pos feedback offset adjust positive input. the output shifts by 100% (typ) of the differential input voltage appearing between pos and neg when dpslp is low. the common-mode range of pos and neg is 0 to 2v. pos and neg should be generated from resistor dividers from the output. 14 neg feedback offset adjust negative input. the output shifts by 100% (typ) of differential input voltage appearing between pos and neg when dpslp is low. the common-mode range of pos and neg is 0 to 2v. pos and neg should be generated from resistor dividers from the output. 15 fb feedback input. fb is internally connected to both the feedback input and the output of the voltage- positioning op amp (figure 2). connect a resistor between fb and oain- (figure 1) to set the voltage- positioning gain (see the setting voltage positioning section). 16 oain- dual-mode op amp inverting input and op amp disable input. when using the internal op amp for additional voltage-positioning gain (figure 1), connect to the negative terminal of current-sense resistor through a 1k ?% resistor as described in the setting voltage positioning section. connect oain- to v cc to disable op amp. the logic threshold to disable the op amp is approximately v cc - 1v. 17 oain+ op am p n oni nver ti ng inp ut. when usi ng the i nter nal op am p for ad d i ti onal vol tag e- p osi ti oni ng g ai n ( fi g ur e 1) , connect to the p osi ti ve ter m i nal of cur r ent- sense r esi stor thr oug h a r esi stor as d escr i b ed i n the s etti ng v ol tag e p osi ti oni ng secti on. 18 csp positive current-limit input. connect to the positive terminal of the current-sense resistor.
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 15 pin description (continued) pin name function 19 csn negative current-limit input. connect to the negative terminal of the current-sense resistor. 20 dpslp deep-sleep control input. when dpslp is low the system enters the deep-sleep state and the regulator applies the appropriate deep-sleep offset. the max1907a/MAX1981A adds the offset measured at the pos and neg pins to the output. 32 clock cycles after the deep-sleep transition is completed, ddo goes low (see the driver disable and low-power pulse skipping section). another 32 clock cycles later, the max1907a/MAX1981A is allowed to enter pulse-skipping operation. 21?6 d5?0 low-voltage vid dac code inputs. d0 is the lsb, and d5 is the msb of the internal 6-bit vid dac (table 4). the d0?5 inputs do not have internal pullups. these 1v logic inputs are designed to interface directly with the cpu. in all normal active modes (modes other than suspend and boot), the output voltage is set by the vid code indicated by the d0?5 logic-level voltages on d0?5. in suspend mode (sus = high), the decoded state of the four-level s0?2 inputs sets the output voltage. in boot mode (see the power-up sequence section), the decoded state of the four-level b0?2 inputs set the output voltage. 27 ddo driver-disable output. this ttl-logic output can be used to disable the driver outputs on slave-switching regulator controllers. this forces a high-impedance condition and makes it possible for the max1907a/MAX1981A master controller to operate in low current skip mode. ddo goes low 32 r time clock cycles after the max1907a/MAX1981A completes a transition to the suspend mode or deep-sleep voltage (see the driver disable and low-power pulse skipping section). another 30 clock cycles later, the max1907a/MAX1981A enters automatic pulse-skipping operation. 28 pgnd power ground. ground connection for the dl gate driver. 29 dl low-side gate driver output. dl swings from pgnd to v dd . dl is forced high after the max1907a/MAX1981A powers down ( shdn = gnd) or when the controller detects a fault. the MAX1981A does not include overvoltage protection. 30 v dd supply voltage input for the dl gate driver. connect to the system supply voltage (4.5v to 5.5v). bypass to pgnd with a 1? or greater ceramic capacitor, as close to the ic as possible. 31 bst boost flying capacitor connection. an optional resistor in series with bst allows the dh pullup current to be adjusted. 32 lx inductor connection. lx is the internal lower supply rail for the dh high-side gate driver. it connects to the skip-mode zero-crossing comparator. 33 dh high-side gate driver. output swings lx to bst. 34 v+ battery voltage sense connection. used only for pwm one-shot timing. dh on-time is inversely proportional to input voltage over a range of 2v to 28v. 35 sus suspend-mode control input. when sus is high the regulator slews to the suspend voltage level. this level is set with four-level logic signals at the s0?2 inputs. 32 clock cycles after the transition to the suspend- mode voltage is completed, ddo goes low (see the driver disable and low-power pulse skipping section). another 32 clock cycles later, the max1907a/MAX1981A is allowed to enter pulse-skipping operation. 36 syspok system power-good input. primarily, syspok serves as the wired nor junction of the open-drain power- good signals for the v ccp and v ccmch supplies. a falling edge on syspok shuts down the max1907a/MAX1981A and sets the fault latch. toggle shdn or cycle v cc power below 1v to restart the controller.
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 16 ______________________________________________________________________________________ table 1. component selection for standard multiphase applications (figure 1) designation component input voltage range* 8v to 24v vid output voltage (d5?0) 1.308v (d5?0 = 011001) boot voltage (b0?2) 1.004v (b2 = open, b1 = v cc , b0 = gnd) suspend voltage (s0?2) 0.748v (s2 = open, s1 = v cc , s0 = gnd) deep-sleep offset voltage (pos, neg) -50mv maximum load current 40a inductor (per phase) 0.6? sumida cdep134h-0r6, panasonic etqp6f0r6bfa, or bi technologies hm73-30r60 switching frequency 300khz (ton = float) high-side mosfet (n h , per phase) international rectifier (2) irf7811w or siliconix (2) si4892dy * input voltages less than 8v requires additional input capacitance. designation component low-side mosfet (n l , per phase) international rectifier (2) irf7822, fairchild (3) fds7764a, or siliconix (2) si4860dy input capacitor (c in ) (6) 10? 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m output capacitor (c out ) (5) 330? 2.5v panasonic eefue0e331xr current-sense resistor (r sense , per phase) 1.5m panasonic erjm1wtj1m5u schottky diodes (d1, d2, d3) central semiconductor cmpsh-3 pin description (continued) pin name function 37 imvpok open-drain power good output. after output voltage transitions, except during power-up and power-down, if out is in regulation then imvpok is high impedance. imvpok is pulled high whenever the slew-rate control is active (output voltage transitions). imvpok is forced low in shutdown. a pullup resistor on imvpok will cause additional finite shutdown current. imvpok also reflects the state of syspok and includes a 3ms (min) delay for power-up. imvpok is forced high during vid transitions. 38 clken clock enable logic output. this inverted logic output indicates when syspok is high and the output voltage sensed at fb is in regulation. clken is forced low during vid transitions. 39 time slew-rate adjustment pin. connect a resistor from time to gnd to set the internal slew-rate clock. a 235k to 23.5k resistor sets the clock from 64khz to 640khz, f slew = 320khz ? 47k /r time . 40 ton on-time selection control input. this four-level input sets the k-factor value (table 3) used to determine the dh on-time (see the on-time one-shot section). gnd = 1000khz, ref = 550khz, open = 300khz, v cc = 200khz.
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 17 off on bst dh lx dl v dd v cc d0 d1 d2 d3 d4 fb dac inputs (1v logic) ref cref 0.22 f c cc 270pf pgnd v+ cc time r time 28k neg s0 s1 suspend inputs (4-level logic) pos ilim sus mode control r1 1.5k 1% c3 100pf r8 301k 1% r10 200k power ground analog ground (master) analog ground (slave) gnd d5 s2 b0 b1 boot inputs (4-level logic) b2 oain- oain+ csn csp imvpok syspok r13 100k r14 100k r12 100k c2 1 f ton float (300khz) trig cm+ cm- cs+ cs- connect to slave controller for multiphase operation (see figure 1a) connect to slave controller for multiphase operation (see figure 1a) ilim (max1980) limit power-good logic signals r7 100k 1% r6 2.74k 1% r2 750 r4 750 r3 1.0k 1% r5 1.0k 1% r9 49.9k 1% c4 470pf c5 100pf c11 1000pf * lower input voltages require additional input capacitance input* 8v to 24v output l m n h(m) n l(m) r cm c out c bst(m) 0.1 f c in (3) 10 f 25v ceramic r11 10 5v bias supply c1 1 f dd (max1980) ddo shdn dpslp clken max1907a MAX1981A r23 200 r22 200 d1 figure 1. standard multiphase application circuit
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 18 ______________________________________________________________________________________ input* 8v to 24v bst dh lx dl pgnd output gnd cs+ cs- v+ pol limit cm+ cm- ton ilim float (300khz) max1980 ref (master) comp output l s n h(s) n l(s) r cs c bst(s) 0.1 f c in (3) 10 f 25v ceramic c7 0.22 f r15 10 r comp 20k c comp 270pf r17 49.9k 1% r16 200k 1% c8 100pf r18 200 r19 200 r20 200 r21 200 c9 4700pf c10 4700pf trig 5v bias supply v dd v cc c6 1 f cs+ cs- dl (master) connect to max1907a/MAX1981A (see figure 1) ilim (master) ddo (master) cm+ cm- connect to max1907a/MAX1981A (see figure 1) power ground analog ground (master) analog ground (slave) dd * lower input voltages require additional input capacitance d2 d3 figure 1a. standard multiphase application circuit (continued)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 19 detailed description 5v bias supply (v cc and v dd ) the max1907a/MAX1981A require an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebook? 95% efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an external linear regulator. the 5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f sw (q g(low) + q g(high) ) = 10ma to 60ma (typ) where i cc is 1.3ma (typ), f sw is the switching frequen- cy, and q g(low) and q g(high) are the mosfet data sheet? total, gate-charge specification limits at v gs = 5v. v+ and v dd can be tied together if the input power source is a fixed 4.5v to 5.5v supply. if the 5v bias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. free-running, constant on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time, current-mode regulator with voltage feed-forward (figure 2). this architecture relies on the output filter capacitor? esr to act as the current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely propor- tional to input voltage and directly proportional to out- put voltage. another one-shot sets a minimum off-time (400ns, typ). the on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off- time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v+ input, and proportional to the output voltage: t on = k(v fb + 0.075v) / v in where k is set by the ton pin-strap connection (table 3) and 0.075v is an approximation to accommodate the supplier phone website bi technologies 714-447-2345 (usa) www.bitechnologies.com central semiconductor 631-435-1110 (usa) www.centralsemi.com coilcraft 800-322-2645 (usa) www.coilcraft.com coiltronics 561-752-5000 (usa) www.coiltronics.com fairchild semiconductor 888-522-5372 (usa) www.fairchildsemi.com international rectifier 310-322-3331 (usa) www.irf.com kemet 408-986-0424 (usa) www.kemet.com panasonic 847-468-5624 (usa) www.panasonic.com sanyo 408-749-9714 (usa) 65-281-3226 (singapore) www.secc.co.jp siliconix (vishay) 203-268-6261 (usa) www.vishay.com sumida 408-982-9660 (usa) www.sumida.com taiyo yuden 408-573-4150 (usa) 03-3667-3408 (japan) www.t-yuden.com tdk 847-803-6100 (usa) 81-3-5201-7241 (japan) www.component.tdk.com toko 858-675-8013 (usa) www.tokoam.com table 2. component suppliers
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 20 ______________________________________________________________________________________ v dd on-time compute max1907a MAX1981A s r q s r q trig q one-shot internal multiplexers and slew-rate control time d0?5 s0?2 b0?2 pgnd dl bst dh lx cc ton v+ trig q one-shot csp csn ilim on-time minimum off-time ref oain- oain+ neg pos fb v cc ref gnd syspok imvpok ddo sus skip-mode logic power-good logic 0.9 x ref 1.1 x ref fault protection ref (2v) shdn dpslp clken g m g m r-2r divider figure 2. max1907a/MAX1981A functional diagram
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 21 expected drop across the low-side mosfet switch. this algorithm results in a nearly constant switching fre- quency despite the lack of a fixed-frequency clock gen- erator. the benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; 2) the inductor ripple-current operating point remains rela- tively constant, resulting in easy design methodology and predictable output voltage ripple. the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics (?0% at 200khz and 300khz, ?2% at 550khz and 1000khz). on-times at operating points far removed from the conditions specified in the electrical characteristics can vary over a wider range. for exam- ple, the 1000khz setting will typically run about 10% slower with inputs much greater than 5v due to the very short on-times required. on-times translate only roughly to switching frequen- cies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high-side mosfet. resistive losses, including the inductor, both mosfets, output capacitor esr, and pc board copper losses in the output and ground tend to raise the switching frequency at higher output currents. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in pwm mode (sus = low, dpslp = low) and during dynamic output voltage transitions when the inductor current reverses at light or negative load cur- rents. with reversed inductor current, the inductor? emf causes lx to go high earlier than normal, extend- ing the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switch- ing frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pc board resistances; and t on is the on-time calculat- ed by the max1907a/MAX1981A. integrator amplifiers/ output voltage offsets two transconductance amplifiers provide a fine adjust- ment to the output regulation point (figure 2). one amplifier forces the dc average of the feedback volt- age to equal the vid dac setting. the second amplifier is used to create small positive or negative offsets to the feedback voltage, using the pos and neg pins. the feedback amplifier integrates the feedback volt- age, allowing accurate dc output voltage regulation regardless of the output ripple voltage. the feedback amplifier has the ability to shift the output voltage by ?%. the differential input voltage range is at least ?0mv total, including dc offset and ac ripple. the integration time constant can be set easily with one capacitor at the cc pin. use a capacitor value of 47pf to 1000pf (270pf, typ). the pos/neg amplifier is used to add small offsets to the vid dac setting in deep-sleep mode ( dpslp = low). the offset amplifier is summed directly with the feedback voltage, making the offset gain independent of the dac code. this amplifier has the ability to offset the output by ?00mv. to create an output offset, bias pos and neg to a voltage (typically v out or ref) with- in their 0 to 2v common-mode range, and offset them from one another with a resistive divider (figure 1). if v pos is higher than v neg , then the output is shifted in the positive direction. if v neg is higher than v pos , then the output is shifted in the negative direction. the output offset equals the voltage difference from pos to neg. forced-pwm operation (normal mode) during normal mode, when the cpu is actively running (sus = low and dpslp = high), the max1907a/ MAX1981A operates with the low-noise, forced-pwm control scheme. forced-pwm operation disables the zero-crossing comparator, forcing the low-side gate- drive waveform to constantly be the complement of the high-side gate-drive waveform. the benefit of forced- pwm mode is to keep the switching frequency fairly constant. f= sw out drop on in drop drop vv tvv v + () +? () 1 12 ton connection frequency setting (khz) k-factor (?) max k-factor error (%) v cc 200 5 10 float 300 3.3 10 ref 550 1.8 12.5 gnd 1000 1.0 12.5 table 3. approximate k-factor errors
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 22 ______________________________________________________________________________________ forced-pwm operation comes at a cost: the no-load 5v bias supply current remains between 10ma to 40ma, depending on the external mosfets and switching fre- quency. to maintain high efficiency under light load conditions, the max1907a/MAX1981A automatically switches to the low-power pulse skipping control scheme after entering suspend or deep-sleep mode. during all output voltage and mode transitions, the max1907a/MAX1981A uses forced-pwm operation in order to ensure fast, accurate transitions. since forced- pwm operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. the controller main- tains forced-pwm operation for 30 clock cycles (set by r time ) after the controller sets the last dac code value to guarantee the output voltage settles properly before entering pulse-skipping operation. low-power pulse skipping during deep-sleep mode ( dpslp = low) or low-power suspend (sus = high), the max1907a/MAX1981A uses an automatic pulse-skipping control scheme. for deep-sleep mode, when the cpu pulls dpslp low, the max1907a/MAX1981A shifts the output voltage to incorporate the offset voltage set by the pos and neg inputs. the controller pulls the driver-disable output ( ddo ) low 32 r time clock cycles after dpslp goes low. another 30 r time clock cycles later, the max1907a/ MAX1981A enters low-power operation, allowing auto- matic pulse skipping under light loads. when the cpu drives dpslp high, the max1907a/MAX1981A immedi- ately enters forced-pwm operation, forces ddo high, and eliminates the output offset, slewing the output to the operating voltage set by the d0?5 inputs. when either dpslp transition occurs, the max1907a/ MAX1981A forces imvpok high and clken low for 32 r time clock cycles. when entering suspend mode (sus driven high), the max1907a/MAX1981A slews the output down to the suspend output voltage set by so?2 inputs. 32 r time clock cycles after the slew-rate controller reaches the last dac code (see the output voltage transition timing section), the driver-disable output ( ddo ) is asserted low. after another 30 r time clock cycles, the max1907a/MAX1981A enters low-power operation, allowing pulse skipping under light loads. when the cpu pulls sus low, the max1907a/MAX1981A immedi- ately enters forced-pwm operation, forces ddo high, and slews the output up to the operating voltage set by the d0?5 inputs. when either sus transition occurs, the max1907a/MAX1981A blanks imvpok and clken , preventing imvpok from going low and clken from going high. the blanking remains until the slew-rate controller has reached the last dac code and 32 rtime clock pulses have passed. in multiphase applications, the driver-disable signal is used to force one or more slave regulators into a high- impedance state. when the master? ddo output is dri- ven low, the slave controller with driver disable (max1980) forces its dl (slave) and dh (slave) gate drivers low, effectively disabling the slave controller. disabling the slave controller for single-phase opera- tion allows the max1907a/MAX1981A to enter low- power pulse-skipping operation under low-power conditions, improving light-load efficiency. when ddo is driven high, the slave controller (max1980) enables the drivers, allowing normal forced-pwm operation. automatic pulse-skipping switchover in skip mode (sus = high, or dpslp = low), an inherent automatic switchover to pfm takes place at light loads (figure 3). this switchover is effected by a comparator that truncates the low-side switch on-time at the induc- tor current? zero crossing. the zero-crossing compara- tor senses the inductor current across the low-side mosfet. once v lx - vp gnd drops below 4mv (typ), the comparator forces dl low (figure 2 ). this mecha- nism causes the threshold between pulse-skipping pfm and non-skipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation. the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 4) . for a battery range of 8v to 24v, this threshold is relatively constant, with only a minor dependence on battery voltage: where k is the on-time scale factor (table 3). for exam- ple, in the standard application circuit this becomes: the crossover point occurs at a lower value if a swing- ing (soft-saturation) inductor is used. the switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light- load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader effi- 13 33 2068 12 0 1 3 12 0 28 .. . .. . . vs h vv v a ? ? ? ? ? ? ? ? ? ? ? ? ? = i vk l vv v load skip out batt out batt () = ? ? ? ? ? ? ? ? ? ? ? ? ? 2
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 23 ciency vs. load curve, while higher values result in high- er full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. current-limit circuit the current-limit circuit employs a unique ?alley?cur- rent-sensing algorithm that uses a current-sense resis- tor between csp and csn as the current-sensing element (figure 1). if the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle ( figure 2 ). since only the ?alley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resis- tance, inductor value, and battery voltage. when com- bined with the undervoltage protection circuit, this current-limit method is effective in almost every circum- stance. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sink- ing current. the negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with an external resistor-divider at ilim. the current-limit threshold volt- age adjustment range is from 10mv to 150mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ilim. the threshold defaults to 50mv when ilim is connected to v cc . the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signals seen by lx and gnd. place the ic close to the low-side mosfet with short, direct traces, making a kelvin sense connection to the source and drain terminals. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder- ately sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the max1907a/MAX1981A will interpret the mosfet gate as ?ff?while there is actually charge still left on the gate. use very short, wide traces (50 to 100 mils wide if the mosfet is 1in from the device). the dead time at the other edge (dh turning off) is deter- mined by a fixed 35ns internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.5 (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive cou- pling from the drain to the gate of the low-side mosfet when lx switches from ground to v in . applications with high input voltages and long inductive traces may require additional gate-to-source capacitance to ensure fast-rising lx edges do not pullup the dl gate driver, causing shoot-through currents. the capacitive cou- inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out i t = inductor current i limit(valley) = i load(max) 2 - lir 2 () time 0 i peak i load i limit figure 4. "valley" current-limit threshold point
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 24 ______________________________________________________________________________________ pling between lx and dl created by the mosfets gate-to-drain capacitance (c rss ), gate-to-source (c iss -c rss ), and additional board parasitics should not exceed the following minimum threshold voltage: lot-to-lot variation of the threshold voltage may cause problems in marginal designs. typically, adding 4700pf between dl and power ground close to the low-side mosfets greatly reduces coupling. due should not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, adding a resistor less than 5 in series with bst may remedy the problem by increasing the turn-on time of the high- side mosfet without degrading the turn-off time (figure 5). voltage positioning amplifier the max1907a/MAX1981A includes a dedicated oper- ational amplifier for adding gain to the voltage position- ing sense path. the voltage positioning gain allows the use of low-value, current-sense resistors in order to minimize power dissipation. this 3mhz gain-bandwidth amplifier was designed with low offset voltage (70?, typ) to meet the imvp-iv output accuracy requirements. the inverting (oain-) and noninverting (oain+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. the op amp? output is internally connected to the regulator? feedback input (fb). the op amp should be configured as a noninvert- ing, differential amplifier as shown in figure 1. the volt- age positioning slope is set by properly selecting the feedback resistor connected from fb to oain- (see the setting voltage positioning section). for applications using a slave controller, additional differential input resistors (summing configuration) should be connected to the slave? voltage-positioning sense resistor (figure 1). summing together both the master and slave cur- rent-sense signals ensures that the voltage-positioning slope will remain constant when the slave controller is disabled. in applications that do not require voltage-positioning gain, the amplifier can be disabled by connecting the oain- pin directly to v cc . the disabled amplifier? out- put becomes high-impedance, guaranteeing that the unused amplifier will not corrupt the fb input signal. the logic threshold to disable the op amp is approxi- mately v cc - 1v. power-on reset power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and preparing the pwm for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switching, and forces the dl gate driver high (to enforce output overvoltage protec- tion). when v cc rises above 4.25v, the dac inputs are sampled and the output voltage begins to slew to the boot voltage ( table 7 ). for automatic startup, the battery voltage should be present before v cc . if the max1907a/MAX1981A attempts to bring the output into regulation without the battery voltage present, the fault latch will trip. the shdn pin can be toggled to reset the fault latch. input undervoltage lockout during start-up, the v cc uvlo circuitry forces the dl gate driver high and the dh gate driver low, inhibiting switching until an adequate supply voltage is reached. once v cc rises above 4.25v, valid transitions detected at the trigger input initiate a corresponding on-time pulse (see the on-time one-shot section). if the v cc voltage drops below 4.25v, it is assumed that there is not enough supply voltage to make valid deci- sions. to protect the output from overvoltage faults, dl is forced high in this mode to force the output to ground. vv c c gs th in rss iss () < ? ? ? ? ? ? max1907a MAX1981A v dd bst dh lx (r bst )* (c nl )* d bst c bst c byp input (v in ) n h l v dd dl pgnd n l (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (cnl)* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. figure 5. high-side gate-driver boost circuitry
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 25 this results in large negative inductor current and possi- bly small negative output voltages. if v cc is likely to drop in this fashion, the output can be clamped with a schottky diode to pgnd to reduce the negative excursion. shutdown when shdn or syspok goes low, the max1907a/ MAX1981A enters low-power shutdown mode. imvpok is pulled low and clken is driven high immediately. the output voltage ramps down to 0 in 16mv steps at the clock rate set by r time . when the dac reaches the 0 setting, dl goes high, dh goes low, the reference is turned off, and the supply current drops to about 0.1?. when syspok activates the shutdown sequence, the controller also sets the fault latch to prevent the con- troller from restarting. to clear the fault latch and reacti- vate the max1907a/MAX1981A, toggle shdn or cycle v cc power below 1v. when shdn goes high, the reference powers up, and after the reference uvlo is passed, the dac target is evaluated and switching begins. the slew-rate controller ramps up from 0 in 16mv steps to the currently selected boot code value (see the power-up sequence section). there is no traditional soft-start (variable current limit) circuitry, so full output current is available immediately. syspok becomes high-impedance after the reference exceeds its uvlo threshold. dac inputs (d0?5) during normal operation (sus = low), the digital-to-ana- log converter (dac) programs the output voltage using the d0?5 inputs. d0?5 are low-voltage (1v) logic inputs, designed to interface directly with the imvp-iv cpu. do not leave d0?5 unconnected. d0?5 can be changed while the max1907a/MAX1981A is active, ini- tiating a transition to a new output voltage level. change d0?5 together, avoiding greater than 1? skew between bits. otherwise, incorrect dac readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct volt- age level, lengthening the overall transition time. the available dac codes and resulting output voltages (table 5) are compatible with imvp-iv specification. four-level logic inputs ton, b0?2, and s0?2 are four-level logic inputs. these inputs help expand the functionality of the con- troller without adding an excessive number of pins. the four-level inputs are intended to be static inputs. when left open, an internal resistive divider sets the input volt- age to approximately 3.5v. therefore, connect the four- level logic inputs directly to v cc , ref, or gnd when selecting one of the other logic levels. see the electrical characteristics for exact logic-level voltages. power-up sequence the max1907a/MAX1981A is enabled when shdn is driven high (figure 6). first, the reference powers up. once the reference exceeds its undervoltage lockout threshold, the pwm regulator becomes active. the slew- rate controller ramps up the output voltage in 16mv increments to the selected boot code value (b0?2, table 7). the ramp rate is set with the r time resistor (see the output voltage transition timing section). syspok serves as the combined power-good input for v ccp and v cc_mch . once these supplies are within ?0% of their output voltage, their power good outputs become high-impedance, allowing syspok to be pulled high. approximately 50? after the max1907a/ MAX1981A detects a logic high voltage on syspok and the fb voltage reaches the target voltage set by b0?2, the controller pulls clken low and slews the output to the proper operating voltage (see table 4 ). when clken goes low, the max1907a/MAX1981A keeps imvpok low for an additional 3ms (min), guaran- teeing that the cpu has time to start properly. if the max1907a/MAX1981A does not detect a fault, then imvpok will be pulled high once the 3ms timer expires. vid (d0?5) v ccp v core v ccp power-ok v cc_mch syspok imvpok t boot t imvpok -12% -12% v cc_mch power-ok soft-start shdn clken figure 6. power-up sequence timing diagram
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 26 ______________________________________________________________________________________ shdn syspok sus dpslp ddo output voltage operating mode 0xxx0gnd low-power shutdown mode. dl is forced high (v dd ), dh is forced low (lx), and the pwm controller is disabled. the supply current drops to 0.1? (typ). 10 0 x 1 b0?2 (no offset) power-up mode. when enabled, the max1907a/ MAX1981A softly ramps up the output voltage to the selected boot voltage (b0?2, table 7). the controller remains at the boot voltage until syspok is driven high (see the power-up sequence section). 11011 d0?5 (no offset) normal operation. the no-load output voltage is determined by the selected vid dac code (d0?5, table 5). 11000 d0?5 (plus offset) deep-sleep mode. the no-load output voltage is determined by the selected vid dac code (d0?5, table 5) plus the offset voltage set by pos and neg. operation with automatic pwm/pfm switchover for pulse skipping under light loads. 1x 1 x 0 s0?2 (no offset) suspend mode. the no-load output voltage is determined by the selected suspend code (s0?2, table 6). operation with automatic pwm/pfm switchover for pulse skipping under light loads. 10xx0gnd fault mode. the fault latch has been set by either uvp, ovp (max1907a only), thermal shutdown, or a falling edge on syspok. the controller will remain in fault mode until v cc power is cycled or shdn toggled. table 4. operating mode truth table
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 27 d5 d4 d3 d2 d1 d0 output voltage (v) 1 0 0 0 0 0 1.196 1 0 0 0 0 1 1.180 1 0 0 0 1 0 1.164 1 0 0 0 1 1 1.148 1 0 0 1 0 0 1.132 1 0 0 1 0 1 1.116 1 0 0 1 1 0 1.100 1 0 0 1 1 1 1.084 1 0 1 0 0 0 1.068 1 0 1 0 0 1 1.052 1 0 1 0 1 0 1.036 1 0 1 0 1 1 1.020 1 0 1 1 0 0 1.004 1 0 1 1 0 1 0.988 1 0 1 1 1 0 0.972 1 0 1 1 1 1 0.956 1 1 0 0 0 0 0.940 1 1 0 0 0 1 0.924 1 1 0 0 1 0 0.908 1 1 0 0 1 1 0.892 1 1 0 1 0 0 0.876 1 1 0 1 0 1 0.860 1 1 0 1 1 0 0.844 1 1 0 1 1 1 0.828 1 1 1 0 0 0 0.812 1 1 1 0 0 1 0.796 1 1 1 0 1 0 0.780 1 1 1 0 1 1 0.764 1 1 1 1 0 0 0.748 1 1 1 1 0 1 0.732 1 1 1 1 1 0 0.716 1 1 1 1 1 1 0.700 d5 d4 d3 d2 d1 d0 output voltage (v) 0 0 0 0 0 0 1.708 0 0 0 0 0 1 1.692 0 0 0 0 1 0 1.676 0 0 0 0 1 1 1.660 0 0 0 1 0 0 1.644 0 0 0 1 0 1 1.628 0 0 0 1 1 0 1.612 0 0 0 1 1 1 1.596 0 0 1 0 0 0 1.580 0 0 1 0 0 1 1.564 0 0 1 0 1 0 1.548 0 0 1 0 1 1 1.532 0 0 1 1 0 0 1.516 0 0 1 1 0 1 1.500 0 0 1 1 1 0 1.484 0 0 1 1 1 1 1.468 0 1 0 0 0 0 1.452 0 1 0 0 0 1 1.436 0 1 0 0 1 0 1.420 0 1 0 0 1 1 1.404 0 1 0 1 0 0 1.388 0 1 0 1 0 1 1.372 0 1 0 1 1 0 1.356 0 1 0 1 1 1 1.340 0 1 1 0 0 0 1.324 0 1 1 0 0 1 1.308 0 1 1 0 1 0 1.292 0 1 1 0 1 1 1.276 0 1 1 1 0 0 1.260 0 1 1 1 0 1 1.244 0 1 1 1 1 0 1.228 0 1 1 1 1 1 1.212 table 5. output voltage vid dac codes (sus = low)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 28 ______________________________________________________________________________________ s2 s1 s0 output voltage (v) gnd gnd gnd 1.452 gnd gnd ref 1.436 gnd gnd open 1.420 gnd gnd v cc 1.404 gnd ref gnd 1388 gnd ref ref 1.372 gnd ref open 1.356 gnd ref v cc 1.340 gnd open gnd 1.324 gnd open ref 1.308 gnd open open 1.292 gnd open v cc 1.276 gnd v cc gnd 1.260 gnd v cc ref 1.244 gnd v cc open 1.228 gnd v cc v cc 1.212 ref gnd gnd 1.196 ref gnd ref 1.180 ref gnd open 1.164 ref gnd v cc 1.148 ref ref gnd 1.132 ref ref ref 1.116 ref ref open 1.100 ref ref v cc 1.084 ref open gnd 1.068 ref open ref 1.052 ref open open 1.036 ref open v cc 1.020 ref v cc gnd 1.004 ref v cc ref 0.988 ref v cc open 0.972 ref v cc v cc 0.956 s2 s1 s0 output voltage (v) open gnd gnd 0.940 open gnd ref 0.924 open gnd open 0.908 open gnd v cc 0.892 open ref gnd 0.876 open ref ref 0.860 open ref open 0.844 open ref v cc 0.828 open open gnd 0.812 open open ref 0.796 open open open 0.780 open open v cc 0.764 open v cc gnd 0.748 open v cc ref 0.732 open v cc open 0.716 open v cc v cc 0.700 v cc gnd gnd 0.684 v cc gnd ref 0.668 v cc gnd open 0.652 v cc gnd v cc 0.636 v cc ref gnd 0.620 v cc ref ref 0.604 v cc ref open 0.588 v cc ref v cc 0.572 v cc open gnd 0.556 v cc open ref 0.540 v cc open open 0.524 v cc open v cc 0.508 v cc v cc gnd 0.492 v cc v cc ref 0.476 v cc v cc open 0.460 v cc v cc v cc 0.444 table 6. suspend mode dac codes (sus = high)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 29 b2 b1 b0 output voltage (v) gnd gnd gnd 1.708 gnd gnd ref 1.692 gnd gnd open 1.676 gnd gnd v cc 1.660 gnd ref gnd 1.644 gnd ref ref 1.628 gnd ref open 1.612 gnd ref v cc 1.596 gnd open gnd 1.580 gnd open ref 1.564 gnd open open 1.548 gnd open v cc 1.532 gnd v cc gnd 1.516 gnd v cc ref 1.500 gnd v cc open 1.484 gnd v cc v cc 1.468 ref gnd gnd 1.452 ref gnd ref 1.436 ref gnd open 1.420 ref gnd v cc 1.404 ref ref gnd 1.388 ref ref ref 1.372 ref ref open 1.356 ref ref v cc 1.340 ref open gnd 1.324 ref open ref 1.308 ref open open 1.292 ref open v cc 1.276 ref v cc gnd 1.260 ref v cc ref 1.244 ref v cc open 1.228 ref v cc v cc 1.212 b2 b1 b0 output voltage (v) open gnd gnd 1.196 open gnd ref 1.180 open gnd open 1.164 open gnd v cc 1.148 open ref gnd 1.132 open ref ref 1.116 open ref open 1.100 open ref v cc 1.084 open open gnd 1.068 open open ref 1.052 open open open 1.036 open open v cc 1.020 open v cc gnd 1.004 open v cc ref 0.988 open v cc open 0.972 open v cc v cc 0.956 v cc gnd gnd 0.940 v cc gnd ref 0.924 v cc gnd open 0.908 v cc gnd v cc 0.892 v cc ref gnd 0.876 v cc ref ref 0.860 v cc ref open 0.844 v cc ref v cc 0.828 v cc open gnd 0.812 v cc open ref 0.796 v cc open open 0.780 v cc open v cc 0.764 v cc v cc gnd 0.748 v cc v cc ref 0.732 v cc v cc open 0.716 v cc v cc v cc 0.700 table 7. boot-mode dac codes (power-up)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 30 ______________________________________________________________________________________ d0 d1 d2 d3 d4 d5 s0 s1 s2 s0?2 decoder in out b0 b1 b2 b0?2 decoder in out sus syspok suspend mux boot mux out 1 0 1 0 sel sel trig q t syspok one-shot out dac figure 7. internal multiplexers functional diagram
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 31 internal multiplexers the max1907a/MAX1981A has two unique internal dac input multiplexers (muxes) that can select one of three different dac code settings for different proces- sor states. on startup, the controller selects the dac code from the b0?2 input decoder. once syspok goes high and the max1907a/MAX1981A properly reg- ulates to the boot voltage, a second multiplexer selects the dac code from either d0?5 (sus = low) or s0?2 (sus = high), depending on the sus state (figure 7). suspend mode when the processor enters low-power suspend mode, the system uses a lower supply voltage to reduce power consumption. the max1907a/MAX1981A include independent suspend-mode output voltage codes set by the four-level inputs s0?2. when the cpu suspends operation, sus is driven high, overrid- ing the 6-bit vid dac code set by d0?5. the master controller slews the output to the selected suspend- mode voltage. during the transition, the max1907a/ MAX1981A asserts forced-pwm operation until 62 r time clock cycles after the slew-rate controller reach- es the suspend-mode voltage. when sus is low, the output voltage is dynamically controlled by the 6-bit vid dac inputs (d0?5). output voltage transition timing the max1907a/MAX1981A is designed to perform mode transitions in a controlled manner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- age level with the lowest possible peak currents for a given output capacitance. this makes the ic ideal for imvp-iv cpus. at the beginning of an output voltage transition, the max1907a/MAX1981A blanks the imvpok and clken outputs, preventing them from changing states. imvpok and clken remain blanked during the transi- tion and is re-enabled 32 clock cycles after the slew- rate controller has set the final dac code value. the slew-rate clock frequency (set by resistor r time ) must be set fast enough to ensure that the transition is com- pleted within the maximum allotted time. the slew-rate controller transitions the output voltage in 16mv increments during power-up, soft-shutdown, and suspend-mode transitions. the total time for a transition depends on r time , the voltage difference, and the accuracy of the max1907a/MAX1981As?slew-rate clock, and is not dependent on the total output capaci- tance. the greater the output capacitance, the higher the surge current required for the transition. the max1907a/MAX1981A automatically control the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ilim. the transition time is given by: where f slew = 320khz ? 47k / r time , v old is the original dac setting, and v new is the new dac setting. the additional 2 clock cycles on the falling edge time are due to internal synchronization delays. see time frequency accuracy in the electrical characteristics for f slew accuracy. the practical range of r time is 23.5k to 235k corre- sponding to 1.6? to 15.6? per 16mv step. although the dac takes discrete 16mv steps, the output filter makes the transitions relatively smooth. the average inductor current required to make an output voltage transition is: i l ? c out ? 16mv ? f slew output overvoltage protection (max1907a only) the overvoltage protection (ovp) circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the output voltage is continuously monitored for over- voltage. if the actual output voltage exceeds the set output voltage by more than 13% (min), ovp is trig- gered and the circuit shuts down. imvpok is pulled low and clken is driven high immediately. the dl low-side gate-driver output is then latched high until shdn is toggled or v cc power is cycled below 1v. this action turns on the synchronous-rectifier mosfet with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. if the condi- tion that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse will blow. ovp can be defeated through the no fault test mode (see the no fault test mode section). t f vv mv for v ri g t f vv mv for v falling slew slew new old out slew slew old new out ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? 1 16 1 16 2 sin
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 32 ______________________________________________________________________________________ output undervoltage shutdown the output undervoltage protection (uvp) function is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the max1907a/MAX1981A output voltage is under 70% of the nominal value, the pwm is latched off and won? restart until shdn is toggled or v cc power is cycled below 1v. uvp is ignored during output voltage transitions and remains blanked for an additional 32 clock cycles after the controller reaches the final dac code value. uvp can be defeated through the no fault test mode (see the no fault test mode section). thermal fault protection the max1907a/MAX1981A features a thermal fault-pro- tection circuit. when the junction temperature rises above 160?, a thermal sensor activates the fault logic, forces the dl low-side gate-driver high, and pulls the dh high-side gate-driver low. this quickly discharges the output capacitors, tripping the master controller? uvlo protection. toggle shdn or cycle v cc power below 1v to reactivate the controller after the junction temperature cools by 15?. no fault test mode the ovp and uvp protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to disable the ovp, uvp, and thermal shut- down features, and clear the fault latch if it has been set. the no fault test mode is entered by forcing 12v to 15v on shdn . design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range. the maximum value (v in(max) ) must accommodate the worst-case, high-ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery-selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current. there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current- limit circuit. the continuous load current (iload) deter- mines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat- contributing components. modern notebook cpus gen- erally exhibit i load = i load(max) ? 80%. for multi-phase systems, each phase supports a frac- tion of the load, depending on the current balancing. when properly balanced, the load current is evenly dis- tributed among each phase: where is the number of phases. switching frequency. this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v in 2 . the optimum frequen- cy is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. setting slave on-time. the constant on-time control algorithm in the master results in a nearly constant switching frequency despite the lack of a fixed-frequen- cy clock generator. in the slave, the high-side switch on-time is inversely proportional to v+, and directly pro- portional to the compensation voltage (v comp ): where k set by the ton pin-strap connection (table 3). inductor operating point. this choice provides trade- offs between size vs. efficiency and transient response vs. output noise. low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical induc- tor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usu- ally found between 20% and 50% ripple current. t= on k v v comp in ? ? ? ? ? ? ii i load slave load master load () ( ) ==
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 33 inductor selection the switching frequency and operating point (% ripple or lir) determine the inductor value as follows: where is the number of phases. example: = 2, i load(max) = 40a, v in = 12v, v out = 1.3v, f sw = 300khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): where is the number of phases. transient response the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time: where t off(min) is the minimum off-time (see the electrical characteristics ), is the number of phases, and k is from table 3. the amount of overshoot due to stored inductor energy can be calculated as: setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at iload(max) minus half the ripple current; therefore: where i limit(low) equals the minimum current-limit threshold voltage divided by the current-sense resistor (r sense ). for the 50mv default setting, the minimum current-limit threshold is 40mv. connect ilim to v cc for a default 50mv current-limit threshold. in adjustable mode, the current-limit thresh- old is precisely 1/10th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to gnd with ilim connected to the center tap. the external 100mv to 2v adjustment range corresponds to a 10mv to 200mv current-limit threshold. when adjusting the current limit, use 1% tolerance resistors and approxi- mately 10? divider current to prevent a significant increase of errors in the current-limit tolerance. in multi-phase applications, set the slave? current-limit threshold above the max1907a/MAX1981As?current- limit threshold. this configuration ensures that the slave? current-limit circuitry will not disrupt the current balance required for stable multi-phase regulation. when the max1907a/MAX1981A limits the master inductor current, the slave? current-balance circuitry also limits the slave inductor current. however, if the current-balance circuitry fails, the slave controller? cur- rent limit provides back-up overcurrent protection. output capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitor? size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: r v i esr step load max () i i i lir limit low load max load max () > ? ? ? ? ? ? ? ? ? ? ? ? ? () () ? 2 v il cv soar load max out out () () 2 2 v li vk v t cv vv k v t sag load max out in off min out out in out in off min = () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () () 2 2 - ii lir peak load max = () + ? ? ? ? ? ? 2 2 l= 13 12 13 2 12 300 40 0 3 064 .. . . vvv v khz a h ? () = l vvv v f i lir out in out in sw load max = ? () ()
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 34 ______________________________________________________________________________________ in non-cpu applications, the output capacitor? size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tor? esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. for out-of- phase operation, the maximum esr to meet ripple requirements is: the previous equation can be rewritten as the single- phase ripple current minus a correction due to the additional phases: where t trig is the propagation delay between the multi- phase on-times, is the number of phases, and k is from table 3. when operating in-phase, the high-side mosfets turn on together, so the output capacitors must simultaneously support the combined inductor ripple currents of each phase. for in-phase operation, the maximum esr to meet ripple requirements is: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load tran- sients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the ris- ing load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors, in widespread use at the time of publica- tion, have typical esr zero frequencies below 30khz. in the standard application used for inductor selection, the esr needed to support a 30mv p-p ripple is 30mv/(40a ? 0.3) = 2.5m . five 330?/2.5v panasonic sp (type xr) capacitors in parallel provide 2m (max) esr. their typical combined esr results in a zero at 48khz. do not put high-value ceramic capacitors directly across the output without taking precautions to ensure stability. ceramic capacitors have a high-esr zero fre- quency and can cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and fb pin. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ?ools?the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased out- put ripple. however, it can indicate the possible pres- ence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. f f where f rc esr sw esr esr out = 1 2 r v i lir r v fl v v vv esr ripple load max esr ripple sw out in in out ? ? ? ? ? ? ? ? ? ? ? ? () ? () r v i lir v l tt esr ripple load max out on trig () ? ? ? ? ? ? + () ? ? ? ? ? ? ?? () ? 1 r v l vv f v v vt esr ripple in out sw out in out trig ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ?? ? 1
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 35 the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the multi-phase slave controllers operate out-of-phase, staggering the turn-on times of each phase. this mini- mizes the input ripple current by dividing the load cur- rent among independent phases: for out-of-phase operation. when operating the multiphase system in-phase, the high-side mosfets turn on simultaneously, so input capacitors must support the combined input ripple cur- rents of each phase: for in-phase operation. for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the max1907a/MAX1981A are operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either con- figuration, choose an input capacitor that exhibits less than +10? temperature rise at the rms input current for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h . if v in does not vary over a wide range, the minimum power dissipation occurs where the resis- tive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., one or two 8-pin sos, dpak or d 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems can occur. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissi- pation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a ther- mocouple mounted on n h : pd n switching vcfi i h in max rss sw load gate () () = () 2 pd n sistive v v i r h out in load ds on (re ) () = ? ? ? ? ? ? ? ? ? ? ? ? 2 ii vvv v rms load out in out in = () ? ? ? ? ? ? ? ? ? i i vvv v rms load out in out in = ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ? ? ?
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 36 ______________________________________________________________________________________ where c rss is the reverse transfer capacitance of n h and i gate is the peak gate-drive source/sink current (1a, typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied, due to the squared term in the c ? v in 2 ? f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low-battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, it is possible to ?ver design?the circuit to tolerate: where i valley(max) is the maximum ?alley?current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a relatively large heatsink to handle the over- load power dissipation. choose a schottky diode (d1) with a forward voltage low enough to prevent the low- side mosfet body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/(3 ) of the load current. this diode is optional and can be removed if efficiency is not critical. setting voltage positioning voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the processor? power dissipation. when the output is loaded, an internal operational amplifier (figures 2 and 8) increases the signal fed back to the master? feed- back input. the additional gain provided by the op amp allows the use of low-value, current-sense resistors, significantly reducing the power dissipated in the cur- rent-sense resistors rather than connecting the feed- back voltage directly to the current-sense resistor. the load-transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guide- lines. to understand the benefits of dynamically adjust- ing the output voltage, see the voltage positioning and effective efficiency section. ii i lir load valley max load max =+ ? ? ? ? ? ? () () 2 pd n sistive v v i r l out in max load ds on (re ) () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 r cm l m master slave board resistance error comparator r f l s r cs = r cm max1907a MAX1981A r a r b r a r b oain+ oain- fb figure 8. voltage positioning gain
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 37 the voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (r sense = r cm = r cs ) connected between the inductors and output capacitors, as shown in figure 8. the voltage drop may be determined by the following equation: where is the number of phases summed together. when the slave controller is disabled, the current-sense summation maintains the proper voltage-positioned slope. select the positive input-summing resistors using the following equation: r a = r b ||( r f ) applications information voltage positioning and effective efficiency powering new mobile processors requires careful attention to detail to reduce cost, size, and power dissi- pation. as cpus became more power hungry, it was recognized that even the fastest dc-dc converters were inadequate to handle the transient power require- ments. after a load transient, the output instantly changes by esr cout ? i load . conventional dc-dc converters respond by regulating the output voltage back to its nominal state after the load transient occurs (figure 9). however, the cpu only requires that the out- put voltage remain above a specified minimum value. dynamically positioning the output voltage to this lower limit allows the use of fewer output capacitors and reduces power consumption under load. for a conventional (non-voltage-positioned) circuit, the total voltage change is: v p-p1 = 2 ? (esr cout ? i load ) + v sag + v soar where v sag and v soar are defined in figure 10. setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases (figure 9). so the total voltage change for a voltage-positioned circuit is: v p-p2 = 2 ? (esr cout ? i load ) + v sag + v soar where v sag and v soar are defined in the design procedure section. since the amplitudes are the same for both circuits (v p-p1 = v p-p2 ), the voltage-positioned circuit tolerates twice the esr. since the esr specifica- tion is achieved by paralleling several capacitors, fewer units are needed for the voltage-positioned circuit. an additional benefit of voltage positioning is reduced power consumption at high load currents. since the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r sense . for a nominal 1.4v, 30a output (r load = 46.7m ), reducing the output voltage 7.1% gives an output voltage of 1.3v and an output current of 27.8a. given these values, cpu power consumption is reduced from 42w to 36.1w. the additional power con- sumption of r sense is: 1.5m ? (27.8a) 2 = 1.16w, which results in an overall power savings of: 42w - (36.1w + 1.16w) = 4.7w. in effect, 5.9w of cpu dissipation is saved and the power supply dissipates much of the savings, but both the net savings and the transfer of dissipation away from the hot cpu are beneficial. effective efficiency is defined as the efficiency required of a non-voltage- positioned circuit to equal the total dissipation of a volt- age-positioned circuit for a given cpu operating condition. v r r i r v r r ir vps f b load sense vps f b load sense =+ ? ? ? ? ? ? ? ? ? ? ? ? =+ ? ? ? ? ? ? 1 1 b 1.4v 1.4v a a. conventional converter (50mv/div) b. voltage-positioned output (50mv/div) voltage positioning the output figure 9. voltage positioning the output
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 38 ______________________________________________________________________________________ calculate effective efficiency as follows: 1) start with the efficiency data for the positioned cir- cuit (v in , i in , v out , i out ). 2) model the load resistance for each data point: r load = v out / i out 3) calculate the output current that would exist for each r load data point in a non-positioned applica- tion: i np = v np / r load where v np = 1.6v (in this example). 4) calculate effective efficiency as: effective efficiency = (v np ? i np ) / (v in ? i in ) = cal- culated non-positioned power output divided by the measured voltage-positioned power input. 5) plot the efficiency data point at the non-positioned current, i np . the effective efficiency of voltage-positioned circuits is shown in the typical operating characteristics . one-stage (battery input) vs. two-stage (5v input) applications the max1907a/MAX1981A can be used with a direct battery connection (one stage) or can obtain power from a regulated 5v supply (two stage). each approach has advantages, and careful consideration should go into the selection of the final design. the one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5v supply. due to the high input volt- age, the one-stage approach requires lower dc input currents, reducing input connection/bus requirements and power dissipation due to input resistance. the transient response of the single stage is better due to the ability to ramp the inductor current faster. the total efficiency of a single stage is better than the two-stage approach. the two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipa- tion. the power supply can be placed closer to the cpu for better regulation and lower i 2 r losses from pc board traces. although the two-stage design has slow- er transient response than the single stage, this can be offset by the use of a voltage-positioned converter. ceramic output capacitor applications ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. however, they are also expensive and brittle, and their ultra-low esr characteristic can result in excessively high esr zero frequencies. in addition, their relatively low capac- itance value can cause output overshoot when step- ping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored inductor energy. in some cases, there may be no room for electrolytics, creating a need for a dc-dc design that uses nothing but ceramics. the max1907a/MAX1981A can take full advantage of the small size and low esr of ceramic output capaci- tors in a voltage-positioned circuit. the addition of the positioning resistor increases the ripple at fb, lowering the effective esr zero frequency of the ceramic output capacitor. output overshoot (v soar ) determines the minimum output capacitance requirement (see the output capacitor selection section). often the switching fre- quency is increased to 550khz, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. the efficiency penalty for operating at 550khz is about 2% when compared to the 300khz circuit, primarily due to the high-side mosfet switching losses. v out esr voltage step (i step x r esr ) capacitive soar (dv/dt = i out /c out ) recovery capacitive sag (dv/dt = i out /c out ) i load figure 10. transient response regions
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 39 pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 11). if possible, mount all of the power compo- nents on the top side of the board with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 2) connect all analog grounds to a separate solid cop- per plane, which connects to the gnd pin of the max1907a/MAX1981A. this includes the v cc bypass capacitor, ref bypass capacitor, compen- sation (cc) capacitor, and the resistive-dividers connected to ilim and pos/neg. 3) the master controller should also have a separate analog ground. return the appropriate noise sensi- tive components to this plane. since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in through to power ground master controller max1907a/MAX1981A (master) through to power ground max1980 (slave) connect the exposed pad to analog gnd < 10 through to analog ground power ground (2nd layer) connect gnd and pgnd the controller at one point only as shown power ground (2nd layer) connect the exposed pad to analog gnd inductor inductor c out c out c out power ground output slave controller input input cpu kelvin sense through under-the-sense resistor (refer to evaluation kit) c out c out c out c out c out c in c in c in c in c in c in figure 11. pc board layout example
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 40 ______________________________________________________________________________________ the master to the analog ground in the slave to pre- vent ground offsets. a low value ( 10 ) resistor is sufficient to link the two grounds. 4) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where 1m of excess trace resistance causes a measurable efficiency penalty. 5) keep the high-current, gate-driver traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. 6) csp, csn, oain+, and oain- connections for cur- rent limiting and voltage positioning must be made using kelvin sense connections to guarantee the current-sense accuracy. 7) when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. 8) route high-speed switching nodes away from sen- sitive analog areas (ref, comp, ilim, csp, csn, etc.). make all pin-strap control input connections ( shdn , ilim, b0?2, s0?2, ton) to analog ground or v cc rather than power ground or v dd . layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper- filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate trace must be short and wide (50mils to 100mils wide if the mosfet is 1 inch from the controller ic). 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed as having four separate ground planes: input/output ground (where all the high-power components go), the power ground plane (where the pgnd pin and v dd bypass capacitor go), the master? analog ground plane (where sensitive analog components such as the master? gnd pin and v cc bypass capacitor go), and the slave? analog ground plane (where the slave? gnd pin and v cc bypass capacitor go). the master? gnd plane must meet the pgnd plane only at a single point directly beneath the ic. similarly, the slave? gnd plane must meet the pgnd plane only at a single point directly beneath the ic. the respective master and slave ground planes should connect to the high- power output ground with a short metal trace from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. chip information transistor count: 8713 process: bicmos
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) ______________________________________________________________________________________ 41 5v bias supply (master) input (slave) input output 5v bias supply active voltage positioning imvp-iv cpu current limit current balance and current limit trigger max1907a MAX1981A max1980 typical operating circuit
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) 42 ______________________________________________________________________________________ qfn thin.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1907a/MAX1981A quick-pwm master controllers for voltage- positioned cpu core power supplies (imvp-iv) maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 43 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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